T e c h n i c a l   a p p r o a c h

SEPHY focuses on the development of a mixed-signal Processing ASIC, as one of the technologies identified as a priority on the list of Urgent Actions on Critical Space Technologies.

The detailed actions to be considered and how they are addressed in SEPHY can be summarized are fivefold:

ITAR-free Ethernet PHY transceiver:

The SEPHY Ethernet transceiver is a mixed-signal device developed in Europe and free from restrictions imposed by the International Traffic in Arms Regulations (ITAR).

The physical layer transceiver deals with the transmission and reception of data over the physical medium ensuring reliable communication (see Figure).

Since the PHY interacts directly with the physical signals on the cable it has to contain an analogue front end capable of transmitting and receiving analogue signals.

As the PHY connects to the digital MAC layer, it needs to perform complex digital signal processing and data controlling.

The physical implementation occurs by means of a mixed-signal ASIC. This is a complex semiconductor device that embeds in the same substrate analogue and digital functions.

The device will be 100% compatible with 10/100Base-T Ethernet standard.

Two-fold radiation hardening approach:

The SEPHY transceiver will undergo:

Radiation hardening by design: special circuit design techniques that can be applied at the system, architectural or layout level, e.g.: EDAC, TMR.

Process hardening: modifications during fabrication processes to reduce the impact of radiation on integrated circuits, e.g.: use of specific insulator materials or the modification of doping profiles.

Functional and environmental (radiation) testing:

The SEPHY results will be tested in a radiation environment measuring all the electrical parameters. In particular, Total Ionizing Dose (TID), Single Event Upset (SEU) and Single Event Latch-up (SEL) tests will be performed.

Estimate the overall performance of the space qualified communication system built around the SEPHY device.

Determine the amount of communication errors induced in the system by the radiation effects.

The PHY behavior will be tested with regards to standard Ethernet and Time-Triggered Ethernet functionality.

All tests guarantee that the SEPHY device achieves a high maturity level such that it will be ready for qualification at the end of the project.

Space-qualified manufacturing and packaging:

The chip will achieve manufacturing which is fully compliant with already existing quality standards and reliability requirements.

The chip will be available in space-grade ceramic and plastic packaging to support different customer requests. The package will be Quad Flat type (QFP), with a maximum of 64 pins.

Support European packaging of naked complex multipad dies and mixed ASIC testing capabilities:

The Ethernet PHY will be a mixed-signal device packaged and tested within Europe.